Modern integrated circuits generally comprise a large number of circuit elements. It is desirable to test these circuit elements in order to ensure the proper operation of the integrated circuit. However, the number of test points (that is, locations where signals can be measured) is limited by the number of terminals of the integrated circuit, which are vastly outnumbered by the number of circuit elements to be tested.
Consequently, designers of modern integrated circuits often employ test techniques referred to herein as “scan testing.” According to scan testing, a mode signal can be asserted that causes predetermined storage elements within an integrated circuit to connect serially to form a scan chain. Data can be shifted into, and out of, the scan chain. Before a test begins, a test vector can be shifted into the scan chain to provide a known starting point for the test. At the end of the test, data can be shifted out of the scan chain for analysis. During the test, the mode signal is negated, thereby breaking the scan chain, so that the integrated circuit can be tested in its nominal configuration. The clock signal is then toggled slowly to simulate nominal operation.
However, it is desirable to test integrated circuits with the clock at higher speeds, in order to identify problems that only appear during high-speed operation. That is, at low speed, an integrated circuit should pass most, if not all tests. However, as the clock speed is increased, the integrated circuit will pass fewer of the tests. The failed tests indicate so-called “speed paths,” where portions of the integrated circuit are unable to pass one or more tests at the clock speed tested. It is desirable to locate these speed paths quickly in order to debug the integrated circuit efficiently.